This paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user intervention. We propose to apply this dynamic loop detection to the speculation of multiple threads of control dynamically obtained from a sequential program. Based on the highly predictable behavior of the loops, the history of the past executed loops is used to speculate the future dynamic instruction sequence. The overall objective is to dynamically obtain coarse grain parallelism (at the thread level) that can be exploited by a multithreaded architecture. We show that for a 4-context multithreaded processor, the specul...
Speculative multithreading (SpMT) architecture can ex-ploit thread-level parallelism that cannot be ...
[[abstract]]Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that...
We present a novel processor microarchitecture that relieves three of the most important bottlenecks...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
An architecture that features dynamic multithreading execution of a single program is studied in thi...
The basic idea under speculative parallelization (also called thread-level spec-ulation) [2, 6, 7] i...
In this paper we present a novel processor microarchitecture that relieves four of the most importan...
The traditional single-core processors are being replaced by chip multiprocessors (CMPs) where sever...
This paper proposes a new compiler technique that enables speculative execution of alternative progr...
In this paper we present a novel processor hardware architecture that relieves three of the most imp...
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two thr...
Research on compiler techniques for thread-level loop speculation has so far remained on studying it...
Graduation date: 2009General purpose computer systems have seen increased performance potential thro...
The advent of multicores presents a promising opportunity for speeding up the execution of sequentia...
Speculatively multithreaded processors find parallelism by speculatively fetching and renaming dynam...
Speculative multithreading (SpMT) architecture can ex-ploit thread-level parallelism that cannot be ...
[[abstract]]Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that...
We present a novel processor microarchitecture that relieves three of the most important bottlenecks...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
An architecture that features dynamic multithreading execution of a single program is studied in thi...
The basic idea under speculative parallelization (also called thread-level spec-ulation) [2, 6, 7] i...
In this paper we present a novel processor microarchitecture that relieves four of the most importan...
The traditional single-core processors are being replaced by chip multiprocessors (CMPs) where sever...
This paper proposes a new compiler technique that enables speculative execution of alternative progr...
In this paper we present a novel processor hardware architecture that relieves three of the most imp...
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two thr...
Research on compiler techniques for thread-level loop speculation has so far remained on studying it...
Graduation date: 2009General purpose computer systems have seen increased performance potential thro...
The advent of multicores presents a promising opportunity for speeding up the execution of sequentia...
Speculatively multithreaded processors find parallelism by speculatively fetching and renaming dynam...
Speculative multithreading (SpMT) architecture can ex-ploit thread-level parallelism that cannot be ...
[[abstract]]Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that...
We present a novel processor microarchitecture that relieves three of the most important bottlenecks...