An architecture that features dynamic multithreading execution of a single program is studied in this dissertation. Threads are created automatically by hardware at procedure and loop boundaries and executed speculatively on a simultaneous multithreading pipeline. Data prediction is used to alleviate dependency constraints and enable lookahead execution of the threads. A two-level hierarchy significantly enlarges the instruction window. Selective recovery from the second level instruction window takes place after a midspredicted input to a thread is corrected. The second level is slower to access but has the advantage of large storage capacity. We show several advantages of this architecture: (1) it increases a superscalar’s execution throu...
Simultaneous multithreading is a technique that permits multiple independent threads to issue multip...
Abstract—We have proposed an auto-memoization processor. This processor automatically and dynamicall...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Graduation date: 2007Dynamic multithreaded processors attempt to increase the performance of a singl...
In this paper we present a novel processor hardware architecture that relieves three of the most imp...
In this paper we present a novel processor microarchitecture that relieves four of the most importan...
We present a novel processor microarchitecture that relieves three of the most important bottlenecks...
The performance of a concurrent multithreaded architectural model, called superthreading [15), is st...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
To reduce the effect of thread overheads when executing small threads in speculative mul-tithreading...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
In this paper, we describe a two-dimensional concurrent multithreaded architecture which combines ag...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
Simultaneous multithreading is a technique that permits multiple independent threads to issue multip...
Simultaneous multithreading is a technique that permits multiple independent threads to issue multip...
Abstract—We have proposed an auto-memoization processor. This processor automatically and dynamicall...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Graduation date: 2007Dynamic multithreaded processors attempt to increase the performance of a singl...
In this paper we present a novel processor hardware architecture that relieves three of the most imp...
In this paper we present a novel processor microarchitecture that relieves four of the most importan...
We present a novel processor microarchitecture that relieves three of the most important bottlenecks...
The performance of a concurrent multithreaded architectural model, called superthreading [15), is st...
This paper analyzes the basic design issues of multithreaded processors and discusses how they may r...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
To reduce the effect of thread overheads when executing small threads in speculative mul-tithreading...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
In this paper, we describe a two-dimensional concurrent multithreaded architecture which combines ag...
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This...
Simultaneous multithreading is a technique that permits multiple independent threads to issue multip...
Simultaneous multithreading is a technique that permits multiple independent threads to issue multip...
Abstract—We have proposed an auto-memoization processor. This processor automatically and dynamicall...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...