Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-ra...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
Field Programmable Gate Arrays (FPGAs) belong to a class of semiconductor devices whose hardware can...
We consider the problem of scheduling the operations of a data flow graph in a reconfigurable comput...
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possibl...
Reconfigurable computing applications have traditionally had the exclusive use of the field programm...
Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that...
Reconfigurable computing combines the benefits of both software and reconfigurable hardware implemen...
An abstract of the thesis of Lan Su submitted to The University of Manchester Faculty of Engineering...
In this paper, we present a hardware-software co-synthesis system, called MOGAC, that partitions and...
Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous ...
The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case ...
In this paper, we present a novel design methodology for synthesizing multiple configurations (or mo...
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems (HRCS) w...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the func...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
Field Programmable Gate Arrays (FPGAs) belong to a class of semiconductor devices whose hardware can...
We consider the problem of scheduling the operations of a data flow graph in a reconfigurable comput...
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possibl...
Reconfigurable computing applications have traditionally had the exclusive use of the field programm...
Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that...
Reconfigurable computing combines the benefits of both software and reconfigurable hardware implemen...
An abstract of the thesis of Lan Su submitted to The University of Manchester Faculty of Engineering...
In this paper, we present a hardware-software co-synthesis system, called MOGAC, that partitions and...
Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous ...
The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case ...
In this paper, we present a novel design methodology for synthesizing multiple configurations (or mo...
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems (HRCS) w...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the func...
Reconfigurable Computers (RC) can provide significant performance improvement for domain application...
Field Programmable Gate Arrays (FPGAs) belong to a class of semiconductor devices whose hardware can...
We consider the problem of scheduling the operations of a data flow graph in a reconfigurable comput...