In this paper, we present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable core that can be used in embedded systems. Recent portable applications require reconfigurability of a system along with efficiency in terms of power, perfor-mance, and area. The field programmable gate arrays (FPGAs) provide a reconfigurable platform; however, they are slower in speed with significantly higher power and area than achievable by a customized application-specific integrated circuits (ASIC). Implementation of a system in either FPGA or ASIC represents a trade-off between programmability and design efficiency. In this work, we have developed techniques to realize efficient reconfigurable cores for ...
Low power consumption and high computational performance are two important processor design goals fo...
Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadli...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a high-level synthesis...
We present a novel design methodology for synthesiz-ing multiple configurations (or modes) into a si...
This thesis studies the design of an architectural platform for realizing a set of selected applicat...
International audienceIn a mobile society, more and more devices need to continuously adapt to chang...
In a mobile society, more and more devices need to continuously adapt to changing environments. Such...
Tailored to run domain-specific applications under very strict constraints on, for example, real-tim...
We present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In ...
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possibl...
By shrinking feature sizes, deep-submicron technology is enabling the design of systems with increas...
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute spe...
Field programmable gate array (FPGA) processing units present considerably higher programming flexib...
International audienceIn this paper, we propose a design methodology for implementing a multimode (o...
With the continued progress in VLSI technologies, we can integrate numerous cores in a single billio...
Low power consumption and high computational performance are two important processor design goals fo...
Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadli...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a high-level synthesis...
We present a novel design methodology for synthesiz-ing multiple configurations (or modes) into a si...
This thesis studies the design of an architectural platform for realizing a set of selected applicat...
International audienceIn a mobile society, more and more devices need to continuously adapt to chang...
In a mobile society, more and more devices need to continuously adapt to changing environments. Such...
Tailored to run domain-specific applications under very strict constraints on, for example, real-tim...
We present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In ...
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possibl...
By shrinking feature sizes, deep-submicron technology is enabling the design of systems with increas...
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute spe...
Field programmable gate array (FPGA) processing units present considerably higher programming flexib...
International audienceIn this paper, we propose a design methodology for implementing a multimode (o...
With the continued progress in VLSI technologies, we can integrate numerous cores in a single billio...
Low power consumption and high computational performance are two important processor design goals fo...
Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadli...
MOODS (Multiple Objective Optimisation in Data and control path Synthesis) is a high-level synthesis...