SuperDLX - A Generic Superscalar Simulator

The objective of this document is to present superDLX, a cycle by cycle superscalar simulator using the DLX instruction set. The simulator was developed as a Master's project, under the supervision of Professor Gao, for the ACAPS (Advanced Compiler, Architectures and Parallel Systems) laboratory of McGill University. This superscalar simulator achieves the most aggressive instruction issue policy: out-oforder issue with out-of-order completion. To implement such instruction processing, several powerful hardware mechanisms were selected: an instruction window, from where instructions issue out of order to multiple functional units; a reorder buffer, where storage conflicts are resolved. To sustain the processor execution rate, branch prediction is performed, which enables the issue logic to dynamically schedule instructions past conditional branches. Also, memory access is optimized, with the use of load and store buffers. The first part of this document outlines some superscalar concep..