Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-passingcommunications network. This interpretive layer is responsible for data location, data movement, and cache coherence. It uses patterns of communication that benefit common programming styles, but which are only heuristics. This suggests that certain styles of communication may benefit from direct access to the underlying communications substrate. The Alewife machine, a shared-memory multiprocessor being built at MIT, provides such an interface. The interface is an integral part of the shared memory implementation and affords direct, user-level access to the netw...
. Interoperability in non-sequential applications requires communication to exchange information usi...
Shared-memory and message-passing are two op- posite models to develop parallel computations. The sh...
Current and emerging high-performance parallel computer architectures generally implement one of two...
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is o...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
This paper discusses some of the issues involved in implementing a shared-address space programming ...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
Company X has just expended 50 engineers over the last three years to produce their latest microproc...
The benefits of hardware support for shared memory versus those for message passing are difficult to...
The goal of this paper is to gain insight into the relative performance of communication mechanisms ...
This paper determines the computational strength of the shared memory abstraction (a register) emul...
In this paper the interprocessor communication interface intended for realization of multiprocessor ...
Shared memory systems generally support consumerinitiated communication; when a process needs data,...
Message-passing is a representative communication model in today’s parallel and distributed programm...
. Interoperability in non-sequential applications requires communication to exchange information usi...
Shared-memory and message-passing are two op- posite models to develop parallel computations. The sh...
Current and emerging high-performance parallel computer architectures generally implement one of two...
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is o...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
This paper discusses some of the issues involved in implementing a shared-address space programming ...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
Company X has just expended 50 engineers over the last three years to produce their latest microproc...
The benefits of hardware support for shared memory versus those for message passing are difficult to...
The goal of this paper is to gain insight into the relative performance of communication mechanisms ...
This paper determines the computational strength of the shared memory abstraction (a register) emul...
In this paper the interprocessor communication interface intended for realization of multiprocessor ...
Shared memory systems generally support consumerinitiated communication; when a process needs data,...
Message-passing is a representative communication model in today’s parallel and distributed programm...
. Interoperability in non-sequential applications requires communication to exchange information usi...
Shared-memory and message-passing are two op- posite models to develop parallel computations. The sh...
Current and emerging high-performance parallel computer architectures generally implement one of two...