. We address the problem of developing efficient cache coherence protocols implementing distributed shared memory (DSM) using message passing. A serious drawback of traditional approaches to this problem is that designers are required to state the desired coherence protocol at the level of asynchronous message interactions. We propose a method in which designers express the desired protocol at a high-level using rendezvous communication. These descriptions are much easier to understand and computationally more efficient to verify than asynchronous protocols due to their small state spaces. The rendezvous protocol can also be synthesized into efficient asynchronous protocols. We present our protocol refinement procedure, prove its soundness...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
technical reportWe address the problem of developing efficient cache coherence protocols for use in ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Recently distributed shared memory (DSM) systems have received much attention because such an abstra...
Multiprocessors in which a shared bus is used by the processor to communicate with common memory are...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Multiprocessors in which a shared bus is used by the processors to com-municate with common memory a...
Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
technical reportWe address the problem of developing efficient cache coherence protocols for use in ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Recently distributed shared memory (DSM) systems have received much attention because such an abstra...
Multiprocessors in which a shared bus is used by the processor to communicate with common memory are...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Multiprocessors in which a shared bus is used by the processors to com-municate with common memory a...
Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...