Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to provide basic communication mechanisms and using software to implement cache coherence policies. The exposure of communication mechanisms to software opens many opportunities for enhancing application performance. In this paper we propose a set of communication primitives that are absent from pure cache coherent schemes. The communication primitives, implemented on a communication co-processor, introduce a flavor of message passing and permit protocol optimization, without sacrificing the simplicity of the shared memory systems. To assess the overhead of the software implementation of the primitives and protocols, we compare, via simulation,...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Shared memory provides an attractive and intuitive programming model that makes good use of programm...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
The goal of this work is to explore architectural mechanisms for supporting explicit communication i...
The goal of this work is to explore architectural mechanisms for supporting explicit communication i...
Thesis (Ph. D.)--University of Washington, 1997Two recent trends are affecting the design of medium-...
Shared memory systems generally support consumerinitiated communication; when a process needs data,...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Her...
Shared-memory multiprocessors are becoming increasingly popular as a high-performance, easy to progr...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Shared memory is widely regarded as a more intuitive model than message passing for the development ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Shared memory provides an attractive and intuitive programming model that makes good use of programm...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
The goal of this work is to explore architectural mechanisms for supporting explicit communication i...
The goal of this work is to explore architectural mechanisms for supporting explicit communication i...
Thesis (Ph. D.)--University of Washington, 1997Two recent trends are affecting the design of medium-...
Shared memory systems generally support consumerinitiated communication; when a process needs data,...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Her...
Shared-memory multiprocessors are becoming increasingly popular as a high-performance, easy to progr...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Shared memory is widely regarded as a more intuitive model than message passing for the development ...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Shared memory provides an attractive and intuitive programming model that makes good use of programm...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...