technical reportWe address the problem of developing efficient cache coherence protocols for use in distributed systems implementing distributed shared memory (DSM) using message passing. A serious drawback of traditional approaches to this problem is that the users are required to state the desired coherence protocol at the level of asynchronous message interactions involving request, acknowledge, and negative acknowledge messages, and handle unexpected messages by introducing intermediate states. Proofs of correctness of protocols described in terms of low level asynchronous messages are very involved. Often the proofs hold only for specific configurations and buffer allocations. We propose a method in which the users state the desired p...
In this paper, we present an algorithm that can be used to implement sequential, causal, or cache co...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
The goal of this work is to explore architectural mechanisms for supporting explicit communication...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
Recently distributed shared memory (DSM) systems have received much attention because such an abstra...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Multiprocessors in which a shared bus is used by the processor to communicate with common memory are...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
In this paper, we present an algorithm that can be used to implement sequential, causal, or cache co...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
The goal of this work is to explore architectural mechanisms for supporting explicit communication...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
Recently distributed shared memory (DSM) systems have received much attention because such an abstra...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Multiprocessors in which a shared bus is used by the processor to communicate with common memory are...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
In this paper, we present an algorithm that can be used to implement sequential, causal, or cache co...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
The goal of this work is to explore architectural mechanisms for supporting explicit communication...