In computer systems with large, physically-indexed, direct-mapped caches, a poor mapping from virtual to physical pages causes excessive cache conflict misses. In a previous paper we proposed a simple hardware device, the Cache Miss Lookaside (CML) Buffer, which identifies pages that are suffering from conflict misses. The operating system can use this information to implement a dynamic page mapping policy that resolves conflicts by performing an in-memory copy of one of the conflicting pages, and updating the virtual to physical mappings. In this paper, we propose several dynamic page mapping policies that detect and resolve cache conflicts using hardware available in existing systems, such as a TLB and cache miss counter, to locate possib...
In embedded systems caches are very precious for keeping low the memory bandwidth and to allow emplo...
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance o...
Limited set-associativity in hardware caches can cause conflict misses when multiple data items map ...
This paper describes a method for improving the performance of a large direct-mapped cache by reduci...
The memory system is often the weakest link in the performance of today’s computers. Cache design ha...
This thesis studies the use of software methods to improve memory performance in a heterogeneous cac...
DRAM row-buffers have become a critical level of cache in the memory hierarchy to exploit spatial lo...
Nearly all modern computing systems employ caches to hide the memory latency. Modern processors ofte...
The predictability of memory access patterns in embedded systems can be successfully exploited to de...
Static cache partitioning can reduce inter-application cache interference and improve the composite ...
Modern life demands fast computations. Even the slightest latencies can have severe consequences and...
There is a lack of flexibility in a fixed page location system because every location within a page ...
This paper proposes an optimization by an alternative approach to memory mapping. Caches with low se...
Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
In embedded systems caches are very precious for keeping low the memory bandwidth and to allow emplo...
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance o...
Limited set-associativity in hardware caches can cause conflict misses when multiple data items map ...
This paper describes a method for improving the performance of a large direct-mapped cache by reduci...
The memory system is often the weakest link in the performance of today’s computers. Cache design ha...
This thesis studies the use of software methods to improve memory performance in a heterogeneous cac...
DRAM row-buffers have become a critical level of cache in the memory hierarchy to exploit spatial lo...
Nearly all modern computing systems employ caches to hide the memory latency. Modern processors ofte...
The predictability of memory access patterns in embedded systems can be successfully exploited to de...
Static cache partitioning can reduce inter-application cache interference and improve the composite ...
Modern life demands fast computations. Even the slightest latencies can have severe consequences and...
There is a lack of flexibility in a fixed page location system because every location within a page ...
This paper proposes an optimization by an alternative approach to memory mapping. Caches with low se...
Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
In embedded systems caches are very precious for keeping low the memory bandwidth and to allow emplo...
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance o...
Limited set-associativity in hardware caches can cause conflict misses when multiple data items map ...