ScratchPad Memory (SPM) is highly adopted in real-time systems as it exhibits a predictable behaviour. SPM is software-managed by explicitly inserting instructions to move code and data transfers between the SPM and the main memory. However, it is a tedious job to decide how to manage the SPM and to manually modify the code to insert memory transfers. Hence, an automated compilation tool is essential to efficiently utilize the SPM. Another key problem with SPM is the latency suffered by the system due to memory transfers. Hiding this latency is important for high-performance systems. In this thesis, we address the problems of managing SPM and reducing the impact of memory latency. To realize the automation of our work, we develop a compilat...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
In recent years, the real-time community has produced a variety of approaches targeted at managing o...
abstract: Cyber-physical systems and hard real-time systems have strict timing constraints that spec...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
Abstract—Hardware-managed caches introduce large amounts of timing variability, complicating real-ti...
Multicore systems will continue to spread in the domain of real-time embedded systems due to the inc...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
To improve the execution time of a program, parts of its instructions can be allocated to a fast Scr...
In resource-constrained real-time embedded systems, scratchpad memory (SPM) is utilized in place of...
Multi-core systems using ScratchPad Memories (SPMs) are attractive architectures for executing time-...
abstract: Caches have long been used to reduce memory access latency. However, the increased complex...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
In recent years, the real-time community has produced a variety of approaches targeted at managing o...
abstract: Cyber-physical systems and hard real-time systems have strict timing constraints that spec...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
Abstract—Hardware-managed caches introduce large amounts of timing variability, complicating real-ti...
Multicore systems will continue to spread in the domain of real-time embedded systems due to the inc...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
To improve the execution time of a program, parts of its instructions can be allocated to a fast Scr...
In resource-constrained real-time embedded systems, scratchpad memory (SPM) is utilized in place of...
Multi-core systems using ScratchPad Memories (SPMs) are attractive architectures for executing time-...
abstract: Caches have long been used to reduce memory access latency. However, the increased complex...
The design of future high-performance embedded systems is hampered by two problems: First, the requi...
CASES 2010 : International Conference on Compilers, Architecture, and Synthesis for Embedded System...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...