This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withstand non-ionizing energy losses (NIEL) of up few 1016 n/cm 2 and up to 500 Mrad total ionization doses (TID). The design of the driver is optimized for a TID exceeding 500 Mrad, for a target bit rate of 10 Gbps. The driver uses a CML (Current Mode Logic) architecture. A cascode architecture is adopted in the last stage to increase the driving voltage. Two driver designs have been implemented, the largest sizing 347 × 180 μm2 layout area and about 170 mW predicted power consumption at 500 Mrad. The ASIC has been submitted to foundry in May 2018
This paper presents the design and experimental verification of two drivers designed to be compliant...
The paper presents the design and the performance characterization, through system-level bit error r...
The paper presents the design and the performance characterization, through system-level bit error r...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a hig...
This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a hig...
Radiations in harsh environments can significantly affects the performance of the silicon devices. T...
Radiations in harsh environments can significantly affects the performance of the silicon devices. T...
The aim of this work is to present the analysis, design, and implementation of an integrated optical...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
The paper presents the design and the performance characterization, through system-level bit error r...
The paper presents the design and the performance characterization, through system-level bit error r...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withst...
This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a hig...
This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a hig...
Radiations in harsh environments can significantly affects the performance of the silicon devices. T...
Radiations in harsh environments can significantly affects the performance of the silicon devices. T...
The aim of this work is to present the analysis, design, and implementation of an integrated optical...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
This paper presents the design and experimental verification of two drivers designed to be compliant...
The paper presents the design and the performance characterization, through system-level bit error r...
The paper presents the design and the performance characterization, through system-level bit error r...