The paper describes, first, a technique to automatically generate extended finite state machines (EFSMs) and high-level decision diagrams (HLDDs) from HDL descriptions. Then, these two paradigms are exploited inside a functional test pattern generator. The goal is to combine the beneficial properties of the above paradigms using EFSMs for targeting control FSM transitions and variable-oriented HLDDs for targeting bit-coverage faults in the data variables, respectively. Experimental results show that combining the two computational models in a functional ATPG yields indeed in higher fault coverage
In this paper we generate conformance test cases for a communication protocol modeled in an EFSM(Ext...
The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-tra...
The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influe...
This paper describes a functional test pattern generator which exploits two different paradigms: hig...
A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state...
This paper presents a functional ATPG framework which exploits the extended finite state machine (EF...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
It is a common opinion that semi-formal verification offers a good compromise between speed and exha...
Control-dominated architectures are usually described in a hardware description language (HDL) by me...
The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is appl...
Recently, a number of works have been published on implementing assignment decision diagram models c...
The paper presents an automatic procedure for generating a particular kind of extended finite state ...
The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by explo...
Functional testing of HDL specifications is one of the most promising approaches for the verificatio...
The EFSM paradigm can be efficiently adopted to model complex designs without incurring in the state...
In this paper we generate conformance test cases for a communication protocol modeled in an EFSM(Ext...
The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-tra...
The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influe...
This paper describes a functional test pattern generator which exploits two different paradigms: hig...
A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state...
This paper presents a functional ATPG framework which exploits the extended finite state machine (EF...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
It is a common opinion that semi-formal verification offers a good compromise between speed and exha...
Control-dominated architectures are usually described in a hardware description language (HDL) by me...
The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is appl...
Recently, a number of works have been published on implementing assignment decision diagram models c...
The paper presents an automatic procedure for generating a particular kind of extended finite state ...
The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by explo...
Functional testing of HDL specifications is one of the most promising approaches for the verificatio...
The EFSM paradigm can be efficiently adopted to model complex designs without incurring in the state...
In this paper we generate conformance test cases for a communication protocol modeled in an EFSM(Ext...
The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-tra...
The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influe...