Add to ORKGThe paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults
Many high-level fault models have been proposed in the past to perform verification at functional le...
Aim of this paper is the analysis of different functional fault models for multi-level implementatio...
The paper describes, first, a technique to automatically generate extended finite state machines (EF...
It is a common opinion that semi-formal verification offers a good compromise between speed and exha...
This paper presents a functional ATPG framework which exploits the extended finite state machine (EF...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state...
The design of a finite state machine can be verified by simulating all its state transitions. Typica...
The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by explo...
This paper introduces and evaluates functional fault models for test pattern generation of sequentia...
Many high-level fault models have been proposed in the past to perform verification at functional le...
This paper describes a functional test pattern generator which exploits two different paradigms: hig...
In this paper we present a novel approach for functional verification of programmable devices. The p...
The paper presents an automatic procedure for generating a particular kind of extended finite state ...
The feasibility of generating high quality functional test vectors for sequential circuits using the...
Many high-level fault models have been proposed in the past to perform verification at functional le...
Aim of this paper is the analysis of different functional fault models for multi-level implementatio...
The paper describes, first, a technique to automatically generate extended finite state machines (EF...
It is a common opinion that semi-formal verification offers a good compromise between speed and exha...
This paper presents a functional ATPG framework which exploits the extended finite state machine (EF...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state...
The design of a finite state machine can be verified by simulating all its state transitions. Typica...
The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by explo...
This paper introduces and evaluates functional fault models for test pattern generation of sequentia...
Many high-level fault models have been proposed in the past to perform verification at functional le...
This paper describes a functional test pattern generator which exploits two different paradigms: hig...
In this paper we present a novel approach for functional verification of programmable devices. The p...
The paper presents an automatic procedure for generating a particular kind of extended finite state ...
The feasibility of generating high quality functional test vectors for sequential circuits using the...
Many high-level fault models have been proposed in the past to perform verification at functional le...
Aim of this paper is the analysis of different functional fault models for multi-level implementatio...
The paper describes, first, a technique to automatically generate extended finite state machines (EF...