A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

International audienceCoarse-grained programmable systolic hardware architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their reusability. An automated mapping methodology is required to add a reusability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable ar-chitectures. We use a Directed Acyclic Graph to express the task and data dependency of the application as well as hardware resources organization. We demonstrate that our approach can map different applications to a complex architecture such as Morphological Co-Processor Unit and provide latency estimation of the final implementation. This approach could be considered as base for design space exploration and optimisation