Design of Reconfigurable Circuit for Image Decoding

Face recognition technology is increasely present in daily live. Video surveillance is one of its important applications. An essential step of monitoring is obtaining the original image from the compressed data transmitted. This work is done by the image decoder. Real-time processing puts higher requirements on the decoder. The image format camera shot mostly is JPEG, short for Joint Photographic Experts Group. And Portable Network Graphics (PNG) format is widely used on the Internet. Currently JPEG hardware decoding is mature but PNG decoding is mostly done by the software. Therefore, designing a high performance decoder which is able to decode a variety of image formats is particularly important. This thesis firstly introduces the current status of the JPEG and PNG decoders. Encoding theories of JPEG and PNG are introduced after that. After analyzing their decoding steps, the overall hardware structure of the decoder is designed. The decoder is divided into several modules and implemented with VHDL. Finally, the decoder is simulated and verified with a number of test images. The results show the decoder can decode the images correctly and restore their orignal pixel arrays. This thesis designs a reconfigurable image decoder which can decode the JPEG and PNG images continuously. The decoder only supports baseline JPEG and two image types of PNG. An improved Canonical Huffman Table (CHT) algorithm is applied in the huffman decoding module and a high efficient pipeline with ping-pong buffers is designed in the Inverse Discrete Cosine Transform (IDCT) module. The decoder is implemented on the Virtex-7 VC709 FPGA at the operating frequency of 200MHz. This decoder performs decompression of 1920×1080 pixels image with a speed of 64 fps for JPEG and 22 fps for PNG.Siirretty Doriast