FPGA implementation of the JPEG2000 MQ decoder

As digital imaging techniques continue to advance, new image compression standards are needed to keep the transmission time and storage space low for increasing image sizes. The Joint Photographic Expert Group (JPEG) fulfilled this need with the ratification of the JPEG2000 standard in December of 2000. JPEG2000 adds many features to image compression technology but also increases the computational complexity of traditional decoders. To mitigate the added computational complexity, the committee developed the JPEG2000 algorithm to process parts in parallel, increasing the benefits of implementing the algorithm in application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). A flexible FPGA implementation of the MQ Decoder, the core component of the JPEG2000 decoding algorithm, is presented in this paper that successfully increases the throughput beyond previous designs