Vector supercomputers, which can process large amounts of vector data efficiently, are among the fastest computers available today. For efficient memory access, these machines use interleaved memories in which sets of consecutive addresses are assigned to separate memory banks. However, when several memory requests access the same bank simultaneously, they interfere with one another causing a significant performance loss. Our thesis addresses this problem of memory interference in vector computers with the goal of analyzing the behavior of current interleaved memory designs and finding ways in which higher performance can be achieved. Using an analytical model for modular interleaved memories, we first derive a new and complete set of condi...
Memory system efficiency is crucial for any processor to achieve high performance, especially in the...
The high latency of memory accesses is one of the factors that most contribute to reduce the perform...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
Interleaved memories are often used to provide the high bandwidth needed by multiprocessors and high...
On many commercial supercomputers, several vector register processors share a global highly interlea...
Most existing analytical models for memory interference generally assume random bank selection for e...
Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engi...
The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnectio...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
This paper presents mathematical foundations for the design of a memory controller subcomponent that...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
The performance of a vector processor accessing vectors is strongly dependent on the conflicts produ...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locali...
A number of vector supercomputers feature very large memories. Unfortunately the large capacity memo...
Memory system efficiency is crucial for any processor to achieve high performance, especially in the...
The high latency of memory accesses is one of the factors that most contribute to reduce the perform...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
Interleaved memories are often used to provide the high bandwidth needed by multiprocessors and high...
On many commercial supercomputers, several vector register processors share a global highly interlea...
Most existing analytical models for memory interference generally assume random bank selection for e...
Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engi...
The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnectio...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
This paper presents mathematical foundations for the design of a memory controller subcomponent that...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
The performance of a vector processor accessing vectors is strongly dependent on the conflicts produ...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locali...
A number of vector supercomputers feature very large memories. Unfortunately the large capacity memo...
Memory system efficiency is crucial for any processor to achieve high performance, especially in the...
The high latency of memory accesses is one of the factors that most contribute to reduce the perform...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...