The purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate a selection of the Perfect Club and Specfp92 programs and compare their execution time on a conventional vector architecture with a single memory port and on a multithreaded vector architecture. We devote an important part of this paper to study the interaction between multi-threading and main memory latency. This paper focuses on maximizing the usage of the memory port, the most expensive resource is typical vector computers. A study of the cost associated with the duplication of the vector register file is also carrie...
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
We are investigating vector-thread architectures which provide competitive performance and efficienc...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
This paper presents data confirming the fact that traditional vector architectures can not reduce th...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
This paper presents data confirming the fact that traditional vector architectures can not reduce th...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level...
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
We are investigating vector-thread architectures which provide competitive performance and efficienc...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
This paper presents data confirming the fact that traditional vector architectures can not reduce th...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
The purpose of this paper is to show that using decoupling techniques in a vector processor, the per...
This paper presents data confirming the fact that traditional vector architectures can not reduce th...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multime...
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level...
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level...
Multithreaded processors, having hardware support for the concurrent execution of fine-grained thre...
We are investigating vector-thread architectures which provide competitive performance and efficienc...