A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips ...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
The growing gap between sustained and peak performance for scientific applications is a well-known p...
Vector architectures have long been the architecture of choice for numerical high performance comput...
In the past, vector supercomputers achieved high performance with long arithmetic pipelines coupled ...
Since the first vector supercomputers in the mid-1970’s, the largest scale applications have traditi...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-Performance Compu...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
The basic architectures of vector and parallel computers and their properties are presented followed...
Vector supercomputers, which can process large amounts of vector data efficiently, are among the fas...
The availability of vector processors capable of sustaining computing rates of 10 to the 8th power a...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
Scientific programs are typically characterized as floating-point intensive loop-dominated tasks wit...
Most existing analytical models for memory interference generally assume random bank selection for e...
Register renaming and out-of-order instruction issue are now commonly used in superscalar processors...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
The growing gap between sustained and peak performance for scientific applications is a well-known p...
Vector architectures have long been the architecture of choice for numerical high performance comput...
In the past, vector supercomputers achieved high performance with long arithmetic pipelines coupled ...
Since the first vector supercomputers in the mid-1970’s, the largest scale applications have traditi...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-Performance Compu...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
The basic architectures of vector and parallel computers and their properties are presented followed...
Vector supercomputers, which can process large amounts of vector data efficiently, are among the fas...
The availability of vector processors capable of sustaining computing rates of 10 to the 8th power a...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
Scientific programs are typically characterized as floating-point intensive loop-dominated tasks wit...
Most existing analytical models for memory interference generally assume random bank selection for e...
Register renaming and out-of-order instruction issue are now commonly used in superscalar processors...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
The growing gap between sustained and peak performance for scientific applications is a well-known p...
Vector architectures have long been the architecture of choice for numerical high performance comput...