Diseño de un ambiente de verificación basado en la metodología UVM para un microprocesador RISC-V 32I

Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2018The electronics engineering school in the Technology Institute of Costa Rica has now an investigation project with other universities in South America and Europe, they have been doing a design of a microprocessor wich is based on RISC-V architecture and its proposed to be used in medical applications to implanted devices as pacemakers or protesis. For that is necessary the implementation of test that verify the performance of any part inside of the microprocessor prior the fabrication. A functional verification environment should exist to send signals as needed to RTL and Reference Models of the device under test, later on it does the comparison between both responses and determines if ther is an error or not, so then if there is a design fault that is causing the issues. To make the verification environment it was necessary to use a methodology that allows the standardization in the design and the implementation, so it’s used the UVM methodology (Universal Verification Methodology) s