Infrastructure and functional correctness in the verification of a RISC-V vector accelerator

When we talk about hardware development, many efforts are made to tape out a bug-free design. The hardware fabrication process costs enormous amounts of money to the companies, so they can not afford to produce faulty hardware. That is why companies have big teams to check that everything is functioning as expected. Verification Teams are the ones in charge of that big duty. Verification could be seen as a trivial task, but colossal efforts must be made to do it correctly. Those are needed to present a reliable environment that produces reliable results and help the Design Team to debug them easily. Techniques such \textit{Universal Verification Methodology}, coverage, assertions are de facto standard in verification. This thesis presents the contributions made in the environment developed for the Verification of a RISC-V Vector Accelerator, made by the Barcelona Supercomputing Center. A UVM testbench capable of sending vector instructions to the \textit{Design Under Test} and once they complete, to compare instruction-by-instruction with the ones provided by the reference model of the design. Moreover, it describes the continuous integration efforts which provided the needed infrastructure to arrive at the current design health