We present a non-speculative solution for a coalescing store buffer in total store order (TSO) consistency. Coalescing violates TSO with respect to both conflicting loads and conflicting stores, if partial state is exposed to the memory system. Proposed solutions for coalescing in TSO resort to speculation-and-rollback or centralized arbitration to guarantee atomicity for the set of stores whose order is affected by coalescing. These solutions can suffer from scalability, complexity, resource-conflict deadlock, and livelock problems. A non-speculative solution that writes out coalesced cachelines, one at a time, over a typical directory-based MESI coherence layer, has the potential to transcend these problems if it can guarantee absence of ...
When supported in silicon, transactional memory (TM) promises to become a fast, simple and scalable ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
This work presents BMW, a new design for speculative implementations of memory consistency models in...
We present a non-speculative solution for a coalescing store buffer in total store order (TSO) consi...
Store misses cause significant delays in shared-memory multiprocessors because of limited store buff...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
In an out-of-order core, the load queue (LQ), the store queue (SQ), and the store buffer (SB) are re...
Abstract. We study two operational semantics for relaxed memory models. Our first formalization is b...
This work presents BMW, a new design for speculative implementations of memory consistency models in...
Abstract. When verifying a concurrent program, it is usual to assume that memory is sequentially con...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
We present a novel framework for defining memory models in terms of two properties: thread-local Ins...
We address the problem of verifying safety properties of concurrent programsrunning over the Total S...
Recent research indicates that hardware can relax memory order speculatively to allow systems that i...
Although the sequential consistency (SC) model is the most intu-itive, processor designers often cho...
When supported in silicon, transactional memory (TM) promises to become a fast, simple and scalable ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
This work presents BMW, a new design for speculative implementations of memory consistency models in...
We present a non-speculative solution for a coalescing store buffer in total store order (TSO) consi...
Store misses cause significant delays in shared-memory multiprocessors because of limited store buff...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
In an out-of-order core, the load queue (LQ), the store queue (SQ), and the store buffer (SB) are re...
Abstract. We study two operational semantics for relaxed memory models. Our first formalization is b...
This work presents BMW, a new design for speculative implementations of memory consistency models in...
Abstract. When verifying a concurrent program, it is usual to assume that memory is sequentially con...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
We present a novel framework for defining memory models in terms of two properties: thread-local Ins...
We address the problem of verifying safety properties of concurrent programsrunning over the Total S...
Recent research indicates that hardware can relax memory order speculatively to allow systems that i...
Although the sequential consistency (SC) model is the most intu-itive, processor designers often cho...
When supported in silicon, transactional memory (TM) promises to become a fast, simple and scalable ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
This work presents BMW, a new design for speculative implementations of memory consistency models in...