Abstract. We study two operational semantics for relaxed memory models. Our first formalization is based on the notion of write-buffers which is pervasive in the memory models literature. We instantiate the (Total Store Ordering) TSO and (Partial Store Ordering) PSO memory models in this framework. Memory models that support more aggres-sive relaxations (eg. read-to-read reordering) are not easily described with write-buffers. Our second framework is based on a general notion of speculative computation. In particular we allow the prediction of func-tion arguments, and execution ahead of time (eg. by branch prediction). While technically more involved than write-buffers, this model is more expressive and can encode all the Sparc family of me...
Abstract. This paper addresses the problem of verifying and correcting programs when they are moved ...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
The integration of transactions into hardware relaxed memory architectures is a topic of current res...
We propose a novel, operational framework to formally describe the semantics of concurrent programs ...
Memory models define an interface between programs written in some language and their implementation...
International audienceModern multicore processor architectures and compilers of shared-memory concur...
For performance reasons, modern multiprocessors implement relaxed memory consistency models that adm...
Abstract. Simple and unified non-operational specifications of the three memory consistency models T...
We address the problem of verifying safety properties of concurrent programsrunning over the Total S...
A memory model for a concurrent imperative programming language specifies which writes to shared var...
We present a novel framework for defining memory models in terms of two properties: thread-local Ins...
Classical model-checking tools verify concurrent programs under the tra-ditional Sequential Consiste...
A memory model for a concurrent imperative programming lan-guage specifies which writes to shared va...
Abstract. When verifying a concurrent program, it is usual to assume that memory is sequentially con...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
Abstract. This paper addresses the problem of verifying and correcting programs when they are moved ...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
The integration of transactions into hardware relaxed memory architectures is a topic of current res...
We propose a novel, operational framework to formally describe the semantics of concurrent programs ...
Memory models define an interface between programs written in some language and their implementation...
International audienceModern multicore processor architectures and compilers of shared-memory concur...
For performance reasons, modern multiprocessors implement relaxed memory consistency models that adm...
Abstract. Simple and unified non-operational specifications of the three memory consistency models T...
We address the problem of verifying safety properties of concurrent programsrunning over the Total S...
A memory model for a concurrent imperative programming language specifies which writes to shared var...
We present a novel framework for defining memory models in terms of two properties: thread-local Ins...
Classical model-checking tools verify concurrent programs under the tra-ditional Sequential Consiste...
A memory model for a concurrent imperative programming lan-guage specifies which writes to shared va...
Abstract. When verifying a concurrent program, it is usual to assume that memory is sequentially con...
AbstractWe extend the notion of Store Atomicity [Arvind and Jan-Willem Maessen. Memory model = instr...
Abstract. This paper addresses the problem of verifying and correcting programs when they are moved ...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
The integration of transactions into hardware relaxed memory architectures is a topic of current res...