Speculative sequential consistency with little custom storage

Recent research indicates that hardware can relax memory order speculatively to allow systems that implement Sequential Consistency (SC) to achieve the performance of systems that relax memory order through software annotation. Such a speculative SC system, called SC++, maintains a history of modified processor and memory state in a custom on-chip queue while memory is speculatively relaxed, and only rolls back the system to an SC-compliant state if there is potential for one processor to observe another processor’s memory accesses out of program order. Unfortunately, the storage requirements for the processor/memory state history vary drastically across applications and systems, demanding a large custom queue to accommodate all applications and systems. Moreover, the history is highly bursty and only accumulates when memory order is speculatively relaxed, there is a long-latency store operation pending, and there is overlapping computation. Therefore, SC++’s large custom queue is typically underutilized. This paper proposes SC++lite, a system derived from SC++ that uses the memory hierarchy to store SC++’s history. The memory hierarchy allows dynamic allocation of storage upon a burst of history, and provides a scalable path for speculative SC systems across a wide range of applications and syste