A LAYOUT AUTOMATOR FOR VLSI CIRCUIT DESIGN USING STANDARD CELLS

This thesis presents the development of a layout automator for VLSI circuit design using a standard cell approach. Technologies currently supported by the layout automator are NMOS and CMOS. Initially, a netlist of the circuit is written in a description language, called Netlisp. It is then processed by a modified design tool Netlist, and a flattened connectivity list of the circuit is obtained. This connectivity list, a description of the dimensions and pin locations of these cells, and a description of the interface node symbols, are then processed by the developed layout automator to obtain the corresponding layout code. The design tool is developed in three stages: placement, routing and code generation. Initial placement of the standard cells is accomplished in two passes: a sequential list placement in the first pass and a feed-through insertion in the second pass. The routing of the standard cells is also implemented in two stages: global routing and channel routing. A method of horizontal compact.ion of the layout by the edge alignment of vias in the routing region is developed and implemented in the design tool. The layout code corresponding to the circuit primitives is generated in the final stage. Currently both KIC and ABCD codes are supported