An Expert System for VLSI Layout

133 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.This thesis addresses the problem of automatic layout generation for the random logic modules in a VLSI chip. We propose a new top-down methodology that eliminates the weakness of a standard cell layout system. Our methodology decomposes the module layout problem into a smaller leaf-cell layout problem and designs the leaf-cells exactly according to their environmental needs.In Chapter 2, we survey the previous approaches to solving this problem. In Chapter 3, we present the overview of LES, which implements our methodology. Chapter 4 describes the analysis subtask, which extracts some useful information from the input description. Chapter 5 describes the placement subtask. Our heuristics is able to produce a better initial placement compared with a random initial placement. In Chapter 6, we present the characterization subtasks, which determines the leaf-cell specifications. Chapter 7 describes a flexible cell generator, which is used as a replacement for the cell library. Chapter 8 describes an optimizer that improves LES's layout quality at the symbolic level.We have collected a set of benchmarks to test out layout methodology. We also compared LES's results against three standard cell systems with different processing technologies. Chapter 9 shows that LES is indeed better than the standard cell approach in producing denser layout.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD