Automatic layout synthesis for high-performance full custom VLSI chips

As the technology advances, millions of transistors can be integrated on a small chip area. With the trend, the physical layout synthesis by human designers becomes costly and error prone due to the various design constraints. Therefore, the demands for intelligent tools have been increasing to create physical layouts for custom logic design. We developed an automatic layout synthesis system for high-performance full custom circuits. In this thesis, we introduce our synthesis system in conjunction with related problems and solutions. Most of the problems in physical layout synthesis, namely, leaf cell construction, partitioning, placement, global routing, detailed routing and transistor/gate sizing, are addressed in our synthesis system. All necessary leaf cells are individually synthesized with customized transistor sizes before placement and tuned after detailed routing. We developed various techniques for the leaf cells synthesis to match layout experts, such as transistor folding, transistor ordering, contact placement and transistor sizing. In partitioning and placement, we concentrated our effort on data path circuits, which is one of the currently popular topics. For detailed routing, a triple-metal-layer over-the-cell router has been developed for a popular platform. Our synthesis system iteratively improves the layout until given requirements are satisfied. We tested our system with various benchmark circuits to measure the performance. Also, a whole chip layout, including bonding pads for DSP circuits, has been synthesized with a hierarchical design scheme.U of I OnlyETDs are only available to UIUC Users without author permissio