Analysis of Control Flow Patterns in the Execution of SPEC CPU2000 Benchmark Programs

Trace cache, an important building block in modem wide-issue processors, buffers and reuses dynamic instruction traces. The selection of relevant traces to the buffered is a critical factor in trace cache performance. The relevance of a trace, determined by its repetition count, is closely tied to the control flow behavior of programs. Hence, we analyse the control flow patterns in the SPEC CPU2000 benchmarks, We detect the loops in the CPU2000 integer benchmarks and study the loop path properties. The loop paths show wide vciation in sizes; sizes ranging from 8 to 100,000 instructions are observed for significant loop paths. In 6 of the 12 benchmarks, loop paths fit within typical L 1 cache sizes. We use the SEQUITUR algorithm to generate reasonably small sets of control flow paths that cover 99% of instruction execution in the benchmarks. These traces cover more than 95% of program execution with different inputs