This paper presents a novel algorithm for temporal partitioning of graphs representing a behavioral description. The algorithm is based on an extension of the traditional static-list scheduling that tailors it to resolve both scheduling and temporal partitioning. The nodes to be mapped into a partition are selected based on a statically computed cost model. The cost for each node integrates communication effects, the critical path length, and the possibility of the critical path to hide the delay of parallel nodes. In order to alleviate the runtime there is no dynamic update of the costs. A comparison of the algorithm to other schedulers and with close-to-optimum results obtained with a simulated annealing approach is shown. The presented a...
The recent introduction of partially-reconfigurable-field-programmable gate arrays (PRFPGAs) has led...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
Heterogeneous system-on-chips (SoC) that include both general-purpose processors and field programma...
Abstract: In this paper, a temporal partitioning algorithm is presented which partitions data flow g...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their fle...
Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and i...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and highlevel...
5th International Conference on Computational Science - ICCS 2005; Atlanta, GA; United States; 22 Ma...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
algorithm for compile-time static scheduling of task graphs onto multiprocessors is proposed. The pr...
Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory...
The recent introduction of partially-reconfigurable-field-programmable gate arrays (PRFPGAs) has led...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
Heterogeneous system-on-chips (SoC) that include both general-purpose processors and field programma...
Abstract: In this paper, a temporal partitioning algorithm is presented which partitions data flow g...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their fle...
Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and i...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and highlevel...
5th International Conference on Computational Science - ICCS 2005; Atlanta, GA; United States; 22 Ma...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
algorithm for compile-time static scheduling of task graphs onto multiprocessors is proposed. The pr...
Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory...
The recent introduction of partially-reconfigurable-field-programmable gate arrays (PRFPGAs) has led...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
Heterogeneous system-on-chips (SoC) that include both general-purpose processors and field programma...