Through a series of mechanical transformation, I show how a three-line recursive Haskell function (Fibonacci) can be translated into a hardware description language -- VHDL -- for efficient execution on an FPGA. The goal of this report is to lay the groundwork for a compiler that will perform these transformations automatically, hence the development is deliberately pedantic
Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the syst...
This paper introduces CλaSH, a novel hardware specification environment, by discussing several non-t...
This thesis contains a collection of work I have performed while working on Dr. Erik Perrins' Effici...
Through a series of mechanical, semantics-preserving transformations, I show how a three-line recurs...
Abstraction in hardware description languages stalled at the register-transfer level decades ago, ye...
This paper presents a design methodology for deriving an FPGA implementation directly from a mathema...
Recursive functions and data types pose significant challenges for a Haskell-to-hardware compiler. D...
To provide high performance at practical power levels, tomorrow’s chips will have to consist primari...
We present an algorithm for unrolling recursion in the Haskell functional language. Adapted from a s...
The amount of resources available on reconfigurable logic devices like FPGAs has seen a tremendous g...
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPG...
Reconfigurable computing is a method of development that provides a developer with the ability to re...
In order to effectively utilize the growing number of resources available on FPGAs, higher level abs...
Abstract. Programs in languages such as Haskell are often datatype-centric and make extensive use of...
Over the last three decades, the number of transistors used in microchips has increased by three ord...
Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the syst...
This paper introduces CλaSH, a novel hardware specification environment, by discussing several non-t...
This thesis contains a collection of work I have performed while working on Dr. Erik Perrins' Effici...
Through a series of mechanical, semantics-preserving transformations, I show how a three-line recurs...
Abstraction in hardware description languages stalled at the register-transfer level decades ago, ye...
This paper presents a design methodology for deriving an FPGA implementation directly from a mathema...
Recursive functions and data types pose significant challenges for a Haskell-to-hardware compiler. D...
To provide high performance at practical power levels, tomorrow’s chips will have to consist primari...
We present an algorithm for unrolling recursion in the Haskell functional language. Adapted from a s...
The amount of resources available on reconfigurable logic devices like FPGAs has seen a tremendous g...
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPG...
Reconfigurable computing is a method of development that provides a developer with the ability to re...
In order to effectively utilize the growing number of resources available on FPGAs, higher level abs...
Abstract. Programs in languages such as Haskell are often datatype-centric and make extensive use of...
Over the last three decades, the number of transistors used in microchips has increased by three ord...
Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the syst...
This paper introduces CλaSH, a novel hardware specification environment, by discussing several non-t...
This thesis contains a collection of work I have performed while working on Dr. Erik Perrins' Effici...
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