In this paper we present work in progress in the development of a complete machine simulator for the UltraSPARC, an imple-mentation of the SPARC V9 architecture. The complexity of the UltraSPARC ISA presents many challenges in developing a reliable and yet reasonably eÆcient implementation of such a simulator. Our implementation includes a heavily object- oriented design for the simulator modules and infrastructure, caching of repeated computations for performance, adding an OS (system call) emulation mode to the simulator and a va-riety of testing strategies. An ultimate and critical goal in constructing such an artifact is to successfully boot an existing operating system from it; we describe techniques implemented so far, and outline the...
Trace driven simulation is a well known technique for performance evaluation of single processor com...
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the...
This report describes sim-kernel, an extension made to the processor simulator SimpleScalar to make ...
This paper presents a novel technique for cycleaccurate simulation of the Central Processing Unit (C...
Annual Technical Conference. all rights reserved. System level simulators allow computer architects ...
An implementation of a system level interpreter of the SPARC V8 instruction set architecture is desc...
In this paper we present Solemn, a new user-level simulation mode for Sparc Sulima, a SPARC V9 compl...
Introduction: This document specifies the SPARC-V9 instruction set syntax, adapted by Bill Clarke fr...
This master's thesis discusses the design and implementation of a simulator for the REPLICA architec...
A simulator is a powerful tool for both hardware and software development. However, implementing an ...
This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit ...
Abstract- The next generation UltraSPARC-I CPU represents a significant step forward in processor pe...
Abstract: There are two paradigms that contribute for increasing the processor’s performance: one ba...
An efficient simulator for the Motorola 88000 at the ISA (Instruction Set Architecture) level is des...
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the...
Trace driven simulation is a well known technique for performance evaluation of single processor com...
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the...
This report describes sim-kernel, an extension made to the processor simulator SimpleScalar to make ...
This paper presents a novel technique for cycleaccurate simulation of the Central Processing Unit (C...
Annual Technical Conference. all rights reserved. System level simulators allow computer architects ...
An implementation of a system level interpreter of the SPARC V8 instruction set architecture is desc...
In this paper we present Solemn, a new user-level simulation mode for Sparc Sulima, a SPARC V9 compl...
Introduction: This document specifies the SPARC-V9 instruction set syntax, adapted by Bill Clarke fr...
This master's thesis discusses the design and implementation of a simulator for the REPLICA architec...
A simulator is a powerful tool for both hardware and software development. However, implementing an ...
This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit ...
Abstract- The next generation UltraSPARC-I CPU represents a significant step forward in processor pe...
Abstract: There are two paradigms that contribute for increasing the processor’s performance: one ba...
An efficient simulator for the Motorola 88000 at the ISA (Instruction Set Architecture) level is des...
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the...
Trace driven simulation is a well known technique for performance evaluation of single processor com...
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the...
This report describes sim-kernel, an extension made to the processor simulator SimpleScalar to make ...