SPARC V9 Instruction Set Specification

Introduction: This document specifies the SPARC-V9 instruction set syntax, adapted by Bill Clarke from the njmctk-v0.5 SPARC-V8 instruction set [1, ch.2]. For more info regarding the special commands used herein, see that code/document. For more information on the New Jersey Machine Code Toolkit, see [2].The context of this specification is with regard to simulating SPARC-V9 cpu’s, and hence may be different to other contexts. All valid instructions in SPARC-V9 ought to be recognised by this specification. Any instruction not directly matched ought to generate an illegal instruction trap when executed or emulated. Some instructions matched may later generate an illegal instruction trap. Any instruction that could cause some other trap and could be detected here (possibly in equations, e.g., the quad-precision floating-point encoding of registers) will have an constructor that accepts these invalid instructions and a constructor that accepts only the truly “valid” instructions. This specification also includes implementation-dependent instructions, such as the VIS instruction-set implemented by the UltraSPARC family of CPUs. This specification also includes special constructors for simulation. For example, all the BPr opcodes are matched with a single BPr constructor with the condition type as an extra field