System Level Interpretation of the SPARC V8 Instruction Set Architecture

An implementation of a system level interpreter of the SPARC V8 instruction set architecture is described. The goal is that the simulator, SimICS, should be sufficiently accurate to run an operating system on top of the simulator. The simulation is performed by direct threaded interpretation of an intermediate code. Simulation of condition codes is performed quickly and can handle all combinations of condition codes. The condition codes are evaluated lazily and unnecessary computations are avoided. Access to registers in a register window is as efficient as in a flat register file. To optimize instructions specialized variants are identified that can be executed faster. SimICS is tested using a comprehensive test suite. The suite exercises the instruction set using interesting combinations of input parameters and operands and compares the result to a reference implementation. A validation of the results is performed with SPEC benchmarks. The result is a stable and correct system level interpreter of SPARC Architecture Version 8 that runs 15 times slower than the real hardware