Single-bit and conventional FIR filter comparison in state-of-art FPGA

The performance/area characteristics of a Sigma Delta Modulated Ternary FIR filter and a conventional FIR filter are compared. The implementation of both filters has been carried out in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. At a similar spectral performance, the ternary FIR filter achieved 40% higher performance than its conventional equivalent using a 12×12 bit multiplier with much lower I/O and a slightly smaller area. This performance ratio was increased to 70% in pipelined mode. Clock speeds in excess of 200MHz at 32 OSR were achieved on a low-cost FPGA and over 400MHz on a high-performance device