Performance-area tradeoffs in the design of a short word length FIR filter

We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9dB at the cost of a doubling in hardware area