Analysis of Booth Multiplier based Conventional and Short Word Length FIR Filter

The optimized implantation of digital filters has remained one of the challenging tasks, for FPGA (Field- Programmable Gate Array) based system designers, due to the involvement of very complex circuitry for multiplication. The multiplier consumes more recourse and hence results in less speed, being not the single step arithmetic operation. One way to carry out these implementations effectively is; to reduce the word length that will increase throughput in view of that. Since decays, SDM (Sigma-Delta Modulation) is used to convert the word length from multi-bit to single bit recurrently. This work is an extension of current trends of using SDM, in the design of Digital FIR (Finite Impulse Response) Filter, which is the most attractive component of DSP (Digital Signal Processor) In this work, we have presented single-bit ternary (0,+1,-1) and multi-bit FIR filter design, using the Booth multiplier technique, on small commercially used FPGA family, provided by Altera. Also, the performance analysis of designed filter with SWL (Short Word Length) using SDM and the conventional one (Multi-bit FIR Filter using general booth multiplier) is carried out. The results indicate that with consuming the resources one third of the conventional design, the sigma delta modulation based multiplier results six times more efficient in terms of achieved frequency, hence sum up the reason of using the sigma delta modulation in about all DSP applications