Unified BIST and functional optimisation in behavioural synthesis

Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the VLSI design cycle. This creates two separate optimisation processes: functional optimisation and BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. In behavioural synthesis, considering testability at such a late stage in the design flow limits the efficient design space exploration as it contradicts the design methodology convergence requirements. It can lead to problems such as exceeding chip area, inability to achieve the required throughput, degraded performance, and inability to apply certain test methods efficiently. Unlike earlier work on "BISTing" data paths, we propose a novel method for inserting and optimising BIST structures at an early stage of High Level Synthesis