A Practical BIST TPG Design Methodology

This paper describes a new technique for the design of BIST TPGs. The TPG design technique identifies compatible circuit inputs that can be connected to the same TPG stage. The key idea is that compatibility between the circuit inputs is determined by analyzing the circuit logic. Unlike pseudoexhaustive testing, circuit inputs that fanout to the same output can be compatible, provided that connecting them to the same TPG stage does not cause any loss of fault coverage. Experimental results show that TPGs designed with the proposed technique achieve 100% stuck-at fault coverage in practical test length without adding extra hardware. This research was funded by NSF Research Initiation Award no. MIP-9210871 1 Introduction Built-in self-test (BIST) is gaining acceptance in the VLSI industry as an alternative to conventional scan-based design-for-testability (DFT) techniques because of its many advantages. Test application under the conventional scan-based DFT techniques requires the u..