A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

International audienceClique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron cliquebased neural network circuit. With a 0.8V power supply and 150nA unitary current, the neuron energy consumption is only 7fJ per synaptic event, i.e. 1330 times less energy than a state-ofthe-art neuron. The network occupies a 41,820µm² silicon area