An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

International audienceClique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron cliquebased neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies 41,820um² silicon area