In this paper, we propose a hardware performance moni-tor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining what data is being evicted from the cache when a miss occurs. We describe how to use this hard-ware support to efficiently determine the cache behavior of application data structures at the source code level. We also present the results of a simulation-based study of this technique, in which we examined the overhead, per-turbation of results, and usefulness of collecting this infor-mation
AbstractAbstract interpretation is a technique for the static detection of dynamic properties of pro...
The growing gap between processor clock speed and DRAM access time puts new demands on software and ...
Worst-Case Execution Time (WCET) is an important metric for programs running on real-time systems, a...
This paper describes the ideas and developments of the project EP-CACHE. Within this project new met...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
This research is part of a co-design project that has the goal of designing hardware syste...
This research is part of a co-design project that has the goal of designing hardware systems to matc...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
With the software applications increasing in complexity, description of hardware is becoming increas...
Prior knowledge of the target application leads to new optimization and customization opportunities ...
Cache memory in processors is used to store temporary copies of the data and instructions a running ...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
Eviction sets are groups of memory addresses that map to the same cache set. They can be used to per...
This paper presents a method for tight prediction of worst-case performance of data caches in high-p...
AbstractAbstract interpretation is a technique for the static detection of dynamic properties of pro...
The growing gap between processor clock speed and DRAM access time puts new demands on software and ...
Worst-Case Execution Time (WCET) is an important metric for programs running on real-time systems, a...
This paper describes the ideas and developments of the project EP-CACHE. Within this project new met...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
This research is part of a co-design project that has the goal of designing hardware syste...
This research is part of a co-design project that has the goal of designing hardware systems to matc...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
With the software applications increasing in complexity, description of hardware is becoming increas...
Prior knowledge of the target application leads to new optimization and customization opportunities ...
Cache memory in processors is used to store temporary copies of the data and instructions a running ...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
Eviction sets are groups of memory addresses that map to the same cache set. They can be used to per...
This paper presents a method for tight prediction of worst-case performance of data caches in high-p...
AbstractAbstract interpretation is a technique for the static detection of dynamic properties of pro...
The growing gap between processor clock speed and DRAM access time puts new demands on software and ...
Worst-Case Execution Time (WCET) is an important metric for programs running on real-time systems, a...