A Technique for Predicting the Effect of Data Cache Associativity

Prior knowledge of the target application leads to new optimization and customization opportunities in embedded system design. Such techniques often lead to design solutions that are better in terms of performance, area, or power. We present a technique that analyzes a given application and statically estimates the number of data cache misses for different associativity values, which is then used in performance and energy estimates. The technique consists of an initial analysis of array reference pairs and determining cache conflict frequency, followed by combining the conflict estimate for all references in a loop nest taken together, incorporating the given associativity value. This analytical estimation is orders of magnitude faster than simulation based techniques and is independent of the data size, leading to significant savings in time in the early stages of embedded system design where decisions on hardware/software trade-offs and architectural customization are taken.