Virtualization of custom logic computations (i.e., by sharing a fixed function across distinct data streams) provides a means of reusing hardware resources, particularly when resources are limited. This is common practice in traditional processors where more than one user can share processor resources. In this paper, we virtualize a custom logic block using C-slow techniques to support fine-grain context-switching. We then develop and present an analytic model for several performance measures (throughput, latency, input queue occupancy) for both fine-grained and coarse-grained context switching (to a secondary memory). Next, we calibrate the analytic performance model with empirical measurements. We then validate the model via discrete-even...
With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more c...
In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks. The ...
Logical simulation is the primary method to verify the correctness of IC designs. However, today’s c...
Virtualization of custom logic computations (i.e., by sharing a fixed function across distinct data ...
Data files supporting paper. Paper abstract: Visualization of logic computations (i.e., by sharing a...
Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulatio...
In this article, we developed a massively parallel gate-level logical simulator to address the ever-...
General purpose parallel processing machines are increasingly being used to speed up a variety of VL...
The high costs associated with logic simulation of large VLSI based systems have led to the need for...
The deterministic nature of conservative simulation makes it possible to conduct an accurate trace-d...
The high costs associated with logic simulation of large VLSI based systems have led to the need for...
Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques...
The high costs associated with logic simulation of large VLSI based circuits has led to the need for...
As the next step towards a computer architecture for parallel execution of logic programs we have im...
In contrast to processors, current reconfigurable devices totally lack programming models that woul...
With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more c...
In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks. The ...
Logical simulation is the primary method to verify the correctness of IC designs. However, today’s c...
Virtualization of custom logic computations (i.e., by sharing a fixed function across distinct data ...
Data files supporting paper. Paper abstract: Visualization of logic computations (i.e., by sharing a...
Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulatio...
In this article, we developed a massively parallel gate-level logical simulator to address the ever-...
General purpose parallel processing machines are increasingly being used to speed up a variety of VL...
The high costs associated with logic simulation of large VLSI based systems have led to the need for...
The deterministic nature of conservative simulation makes it possible to conduct an accurate trace-d...
The high costs associated with logic simulation of large VLSI based systems have led to the need for...
Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques...
The high costs associated with logic simulation of large VLSI based circuits has led to the need for...
As the next step towards a computer architecture for parallel execution of logic programs we have im...
In contrast to processors, current reconfigurable devices totally lack programming models that woul...
With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more c...
In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks. The ...
Logical simulation is the primary method to verify the correctness of IC designs. However, today’s c...