Abstract Parallel Logic Level simulation of VLSI Circuits

In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks. The simulator is written in Maisie, a simulation language developed at UCLA. The unique feature of it is that it allows a simulation model to be executed in either conservative or optimistic modes with minimal changes to the model. It also supports a number of optimizations to reduce both checkpointing and blocking overheads for the corresponding simulation protocol. Maisie also supports a variety of parallel and distributed architectures including a network of workstations. We also have implemented our efficient acyclic multi-way network partitioning algorithm named K-MAFM algorithm, which consistantly outperforms conventional undirected methods. We have evaluated the impact on parallel circuit simulation of different number of partitions with different parallel and sequential simulation algorithms on different number of processors and obtained very interesting and encouraging experimental results on various Boolean networks from the ISCAS85 benchmark circuits. Significant speed-ups are achieved when either optimistic or conservative algorithm is used. We have evaluated and understood the relationship among several important facts of the parallel language system and performance of simulations