Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors

for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the offi-cial policies or endorsements, either expressed or implied, of the Wright Laboratory Avionics Directorate or the U.S. Government. This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalida-tion messages by having a processor automatically invali-date its local copy of a cache block before a conflicting access by another processor. Eliminating invalidation overhead is particularly important under sequential con-sistency, where the latency of invalidating outstanding copies can increase a program’s critical path. DSI is applicable to software, hardware, and hybrid coherence schemes. In this paper we evaluate DSI in the context of hardware directory-based write-invalidate coherence protocols. Our results show that DSI reduces execution time of a sequentially consistent full-map coher-ence protocol by as much as 41%. This is comparable to an implementation of weak consistency that uses a coa-lescing write-buffer to allow up to 16 outstanding requests for exclusive blocks. When used in conjunction with weak consistency, DSI can exploit tear-off blocks—which elimi-nate both invalidation and acknowledgment messages— for a total reduction in messages of up to 26%.