A low-power IF circuit with 5 dB minimum input SNR for GFSK

SUMMARY A low-power low-noise intermediate-frequency (IF) cir-cuit is proposed for Gaussian frequency shift keying (GFSK) low-IF re-ceivers. The proposed IF circuit is realized by an all-analog architecture composed of a couple of limiting amplifiers (LAs) and received signal strength indicators (RSSIs), a couple of band-pass filters (BPFs), a fre-quency detector (FD), a low-pass filter (LPF) and a slicer. The LA and RSSI are realized by an optimized combination of folded amplifiers and current subtractor based rectifiers to avoid the process induced depressing on accuracy. In addition, taking into account the nonlinearity and static cur-rent of rectifiers, we propose an analytical model as an accurate approxima-tion of RSSIs ’ transfer character. An active-RC based GFSK demodulation scheme is proposed, and then both low power consumption and a large dy-namic range are obtained. The chip is implemented with HJTC 0.18 µm CMOS technology and measured under an intermediate frequency of 200 kHz, a data rate of 100 kb/s and a modulation index of 1. The RSSI has a dynamic range of 51 dB with a logarithmic linearity error of less than ±1 dB, and the slope is 23.9 mV/dB. For 0.1 % bit error ratio (BER), the pro-posed IF circuit has the minimum input signal-to-noise ratio (SNR) of 5 dB and an input dynamic range of 55.4 dB, whereas it can tolerate a frequency offset of-3%∼+9.5 % at 6 dB input SNR. The total power consumption is 5.65∼5.89 mW. key words: limiting amplifier (LA), received signal strength indicator (RSSI), demodulator, slicer. 1