A Low-Power All-Digital GFSK Demodulator with Robust Clock Data Recovery ∗

This paper presents an all-digital Gaussian frequency shift keying (GFSK) demodulator with robust clock data recov-ery (CDR) for low-intermediate-frequency (low-IF) receivers in wireless sensor networks (WSN). The proposed demodu-lator can detect and adapt to the intermediate frequency of the received signal automatically. In addition, the CDR can tolerate the frequency deviation of the input clock. An im-plementation of the demodulator with CDR is realized with HJTC 0.18 µm CMOS technology. The chip is designed for GFSK signals with a center frequency of 200 kHz, a modu-lation index of 1 and a data rate of 100 kbps. Experimental results show that the chip consumes 0.53 mA from a 1.8 V power supply, and only a 11 dB input signal to noise ratio (SNR) is required for 10−3 bit error rate (BER). The toler-ance range for IF offset is ±12.5 % at 11 dB input SNR, and the CDR can tolerate frequency deviation of the input clock of ±0.1%