Designers are increasingly utilizing spatial (e.g. custom and reconfigurable) architectures to improve both efficiency and performance in increasingly heterogeneous systems-on-chip. Unfortunately, while such architectures can provide orders of magnitude better efficiency and performance on numeric applications, they exhibit poor performance when implementing sequential, control-flow intensive code. This thesis studies the problem of improving sequential code performance in spatial hardware without sacrificing its inherent efficiency advantage. I propose (a) switching from a statically scheduled to a dynamically scheduled, dataflow execution model, and (b) utilizing a newly developed compiler intermediate representation (IR) designed to expo...
A common approach to decreasing embedded application execution time is creating a homogeneous parall...
Spatial processing of sparse, irregular, double-precision floating-point computation using a single ...
Abstract—A program executing on a spatial computer must be able to react to changes in its environme...
Abstract—While custom (and reconfigurable) computing can provide orders-of-magnitude improvements in...
Spatial computing architectures promise a major stride in performance and energy efficiency over the...
Spatial architecture is a high-performance architecture that uses control flow graphs and data flow ...
For decades, the computational performance of processors has grown at a faster rate than the availab...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved p...
Abstract—We explore the feasibility of using a coarse-grain overlay to transparently and dynamically...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
The difficulty of effectively parallelizing code for multicore processors, combined with the end of ...
reconfigurable computing, power-efficient computation This thesis presents a compilation framework f...
145 pagesWith the pursuit of improving compute performance under strict power constraints, there is ...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
A common approach to decreasing embedded application execution time is creating a homogeneous parall...
Spatial processing of sparse, irregular, double-precision floating-point computation using a single ...
Abstract—A program executing on a spatial computer must be able to react to changes in its environme...
Abstract—While custom (and reconfigurable) computing can provide orders-of-magnitude improvements in...
Spatial computing architectures promise a major stride in performance and energy efficiency over the...
Spatial architecture is a high-performance architecture that uses control flow graphs and data flow ...
For decades, the computational performance of processors has grown at a faster rate than the availab...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved p...
Abstract—We explore the feasibility of using a coarse-grain overlay to transparently and dynamically...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
The difficulty of effectively parallelizing code for multicore processors, combined with the end of ...
reconfigurable computing, power-efficient computation This thesis presents a compilation framework f...
145 pagesWith the pursuit of improving compute performance under strict power constraints, there is ...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
A common approach to decreasing embedded application execution time is creating a homogeneous parall...
Spatial processing of sparse, irregular, double-precision floating-point computation using a single ...
Abstract—A program executing on a spatial computer must be able to react to changes in its environme...