Pipelining is a common method for improving the throughput of a system, especially when the majority of the processing is sequential. Unfortunately when the se-quentiality is broken, a pipelined system suffers additional delay and, most importantly for this work, energy waste which is roughly proportional to the pipeline depth. Stan-dard pipelines cannot be modified once they are built so their depth is fixed. This paper proposes a method that al-lows the dynamic adaptation of the structure of an asyn-chronous pipeline, so that pipeline stages can be merged and split at run-time, allowing greater flexibility. It is based on novel latch controllers that can be configured dynami-cally as ‘normal ’ or ‘collapsed’, i.e. keeping their latches pe...
Pipelining – the technique of separating different stages of a circuit using registers – is a common...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages ...
A method of managing the power consumption of an em-bedded, single-issue processor by controlling it...
We present a technique to automatically synthesize hetero-geneous asynchronous pipelines by combinin...
The minimization of propagation delay between pipeline stages is very important in wave propagation ...
SUMMARY A new pipeline controller based on the Early Acknowl-edgement (EA) protocol is proposed for ...
International audienceThis paper presents two new area-reduced controllers for bundled-data asynchro...
We present a technique to automatically synthesize heterogeneous asynchronous pipelines by combining...
Many approaches recently proposed for high-speed asynchro-nous pipelines are applicable only to line...
This paper presents a new approach for automatically pipelin-ing sequential circuits. The approach r...
With the advance of fabrication technology into the deep sub-micron era process parameter variations...
Recently, optimization techniques have been applied to the problem of minimizing pressure transients...
ISBN : 978-1-4244-2182-4International audienceThis paper introduces a new methodology for optimizing...
In previous work, a pipelined controller had been proposed, which enable better control methods to b...
Pipelining – the technique of separating different stages of a circuit using registers – is a common...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages ...
A method of managing the power consumption of an em-bedded, single-issue processor by controlling it...
We present a technique to automatically synthesize hetero-geneous asynchronous pipelines by combinin...
The minimization of propagation delay between pipeline stages is very important in wave propagation ...
SUMMARY A new pipeline controller based on the Early Acknowl-edgement (EA) protocol is proposed for ...
International audienceThis paper presents two new area-reduced controllers for bundled-data asynchro...
We present a technique to automatically synthesize heterogeneous asynchronous pipelines by combining...
Many approaches recently proposed for high-speed asynchro-nous pipelines are applicable only to line...
This paper presents a new approach for automatically pipelin-ing sequential circuits. The approach r...
With the advance of fabrication technology into the deep sub-micron era process parameter variations...
Recently, optimization techniques have been applied to the problem of minimizing pressure transients...
ISBN : 978-1-4244-2182-4International audienceThis paper introduces a new methodology for optimizing...
In previous work, a pipelined controller had been proposed, which enable better control methods to b...
Pipelining – the technique of separating different stages of a circuit using registers – is a common...
In this paper, we present a novel synchronization approach to support data flow in clockless designs...
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages ...